HMC703LP4E【PDF 21/58 页】IC FRACT-N PLL W/SWEEPR 24QFN

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HMC703LP4E

v02.0813

8 GHz fractional syntHesizer

For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824

978-250-3343 978-250-3373 fax Order On-line at www.hittite.com

Application Support: pll@hittite.com

Figure 34. Single Step Ramp Mode

The user should be aware that the synthesized ramp is subject to normal phase locked loop dynamics. If the loop

bandwidth in use is much wider than the rate of the steps then the locking will be fast and the ramp will have a

staircase shape. If the update rate is higher than the loop bandwidth, as is normally the case, then the loop will not

fully settle before a new frequency step is received. Hence the swept output will have a small lag and will sweep in a

near continuous fashion.

Detailed sweeper configuration

The Following procedure is recommended to configure the frequency sweep in HMC703LP4E:

Lock in fractional mode (Reg 06h[7:5] = 0) to the start frequency (f0).

Program frequency step Reg 0Ah and stop N (Reg 0Ch,Reg 0Dh). Note that stop N must be exactly equal

to start N plus an integer number of steps (Reg 0Ah). If it is not, the sweeper function will not terminate

properly. This normally means rounding the stop N up or down slightly to ensure it falls on a step boundary.

Change Mode to Reg 06h[7:5] = 5,6, or 7 - depending on the desired profile.

Note that the ramp step Reg 0Ah is signed two’s complement. If negative, the first ramp has a negative slope, and

vice-versa.

setting autoseed (Reg 06h[8] = 1) ensures that different sweeps have identical phase profile. This is achieved by

loading the seed (Reg 05h) into the phase accumulator at the beginning of each ramp

setting Reg 06h[22] = 1 ensures identical phase AND quantization noise performance on each sweep by resetting the

entire delta-sigma modulator at the beginning of each ramp.

Note that, while the HMC703LP4E can enforce phase coherence between different frequency sweeps, there will be a

phase discontinuity if the start phase that is programmed in sEED (Reg 05h) is different from the phase state that the

PLL finds itself in at the end of the ramp. This discontinuity can be prevented by tailoring the sweep profile such that

the phase of the PLL at the start of the ramp is equal to phase at the end of the ramp.

Example: Configure a sweep from f0 = 3000 MHz to ff = 3105 MHz in Tramp ≈ 2 ms, with fPD = 50 MHz:

1. Start in fractional mode (Program Reg 06h[7:5] = 0)

1. Calculate Start N and Stop N, Program Start N (Reg 03h,Reg 04h)

Start N = 3000.0 MHz / 50.0 MHz = 60.0

Stop N = 3105.0 MHz / 50.0 MHz = 62.1

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